2020-2021 Sunseeker Telemetry and Lighting System
pmm_Reset_LPMx_5.c
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32 //******************************************************************************
33 // MSP430FR57xx PMM Test
34 // This example shows transitions between a user Reset via the reset button, a
35 // software triggered BOR, a previous LPMx.5 state indicator flag, and entrance
36 // into LPM4.5. Reading the reset interrupt flag from PMMIFG register is equivalent
37 // to reading from reset vector register.
38 //
39 // Upon device power on you will see the following sequence of LED's
40 // X = off
41 // O = on
42 //
43 // _7 = On indicates BOR
44 // _6 = On indicates Reset (from user button)
45 // _5 = on indicates device was previously in LPMx.5 state before the reset
46 // _4 = On indicates device is NOT sleeping. Off means device is in LPM4.5
47 //*******************************************************************************
48 //
49 // 1) Power on device:
50 // X7 X6 X5 O4 LED4 is on, device is running and was not in LPM4.5 mode previously.
51 //
52 // 2) Press User Reset button:
53 //
54 // X7 O6 X5 O4 Device is running and has reset due to RST pin
55 // O7 X6 X5 O4 Device is running and has reset due to a software BOR
56 // X7 X6 X5 X4 Device is now in LPM4.5
57 //
58 // 3) Press User Reset button:
59 // X7 X6 O5 O4 Device is running and was previously in LPM4.5
60 //
61 // 4) Press User Reset button:
62 // Device will restart the sequence beginning at step 2).
63 //
64 //
65 //********************************************************************************
66 #include "driverlib.h"
67 
68 void main(void)
69 {
70  //Stop WDT
71  WDT_A_hold(WDT_A_BASE);
72  //Unlock the GPIO pins.
73  /*
74  * Base Address of PMM,
75  * By default, the pins are unlocked unless waking
76  * up from an LPMx.5 state in which case all GPIO
77  * are previously locked.
78  *
79  */
80  PMM_unlockLPM5();
81  //Set P3.4, 3.5, 3.6, 3.7 as output pins.
82  /*
83 
84  * Select Port 3
85  * Set Pin 4, 5, 6, 7 as output
86  */
87  GPIO_setAsOutputPin(
88  GPIO_PORT_P3,
89  GPIO_PIN4 + GPIO_PIN5 + GPIO_PIN6 + GPIO_PIN7
90  );
91  //Set P3.5, 3.6, 3.7 Low.
92  /*
93 
94  * Select Port 3
95  * Set Pin 5, 6, 7 as Low
96  */
98  GPIO_PORT_P3,
99  GPIO_PIN5 + GPIO_PIN6 + GPIO_PIN7
100  );
101  //Set P3.4 as High.
102  /*
103 
104  * Select Port 3
105  * Set Pin 4 as High
106  */
108  GPIO_PORT_P3,
109  GPIO_PIN4
110  );
111 
112  //Get Interrupt Status from the PMMIFG register.
113  /* Base Address of PMM,
114  * mask:
115  * PMM_BOR_INTERRUPT
116  * PMM_RST_INTERRUPT,
117  * PMM_PMMPORIFG,
118  * PMM_SVSLIFG,
119  * PMM_SVSHIFG
120  * PMM_LPM5_INTERRUPT,
121  * return STATUS_SUCCESS (0x01) or STATUS_FAIL (0x00)
122  */
123  if (PMM_getInterruptStatus(PMM_LPM5_INTERRUPT)) // Was this device in LPMx.5 mode before the reset was triggered?
124  {
125  //Clear Interrupt Flag from the PMMIFG register.
126  /* Base Address of Comparator D,
127  * mask:
128  * PMM_BOR_INTERRUPT
129  * PMM_RST_INTERRUPT,
130  * PMM_PMMPORIFG,
131  * PMM_SVSLIFG,
132  * PMM_SVSHIFG
133  * PMM_LPM5_INTERRUPT,
134  * PMM_ALL
135  */
136  PMM_clearInterrupt(PMM_LPM5_INTERRUPT); // Clear the LPMx.5 flag
138  GPIO_PORT_P3,
139  GPIO_PIN5
140  );
141  }
142 
143  if (PMM_getInterruptStatus(PMM_RST_INTERRUPT)) // Was this reset triggered by the Reset flag?
144  {
145  PMM_clearInterrupt(PMM_RST_INTERRUPT); // Clear reset flag
147  GPIO_PORT_P3,
148  GPIO_PIN6
149  );
150  __delay_cycles(1000000); // to include a visual delay.
151 
152  //Trigger a software Brown Out Reset (BOR)
153  /*
154  * Base Address of PMM,
155  * Forces the devices to perform a BOR.
156  */
157  PMM_trigBOR(); // Software trigger a BOR.
158  }
159 
160  if (PMM_getInterruptStatus(PMM_BOR_INTERRUPT)) // Was this reset triggered by the BOR flag?
161  {
162  PMM_clearInterrupt(PMM_BOR_INTERRUPT); // Clear BOR flag
164  GPIO_PORT_P3,
165  GPIO_PIN7
166  );
167 
168  __delay_cycles(1000000); // to include a visual delay.
170  GPIO_PORT_P3,
171  GPIO_PIN4 + GPIO_PIN7
172  );
173 
174  //Disable SVSH
175  /*
176  * Base Address of PMM,
177  * High-side SVS (SVSH) is disabled in LPM4.5. SVSH is
178  * always enabled in active mode and LPM0/1/2/3/4 and LPM3.5.
179  */
180  PMM_disableSVSH();
181  //Disable SVSL
182  /*
183  * Base Address of PMM,
184  * Low-side SVS (SVSL) is disabled in low power modes.
185  * SVSL is always enabled in active mode and LPM0.
186  */
187  PMM_disableSVSL();
188  //Disable Regulator
189  /*
190  * Base Address of PMM,
191  * Regulator is turned off when going to LPM3/4.
192  * System enters LPM3.5 or LPM4.5, respectively.
193  */
194  PMM_turnOffRegulator();
195  __bis_SR_register(LPM4_bits); // Enter LPM4.5, This automatically locks
196  //(if not locked already) all GPIO pins.
197  // and will set the LPM5 flag and set the LOCKLPM5 bit
198  // in the PM5CTL0 register upon wake up.
199  }
200 
201  while (1)
202  {
203  __no_operation(); // Don't sleep
204  }
205 }
void main(void)
__no_operation()
GPIO_setOutputHighOnPin(GPIO_PORT_LED1|GPIO_PORT_LED2, GPIO_PIN_LED1|GPIO_PIN_LED2)
GPIO_setOutputLowOnPin(GPIO_PORT_LED1|GPIO_PORT_LED2, GPIO_PIN_LED1|GPIO_PIN_LED2)
__delay_cycles(500000)